Most prior art ferroelectric memory devices, such as the memory device 100 shown in FIG. 1, store a single bit of information in a pair of cells 102, 104, each in a different state. For example, a "1" bit may be represented by storing an "up" polarization in ferroelectric capacitor 130 of cell 102 and storing a "down" polarization in ferroelectric capacitor 133 of cell 104. The pair of cells 102-104 is read by enabling word line 106 and then sending a pulse on drive line 108. A sense amplifier 110 at the end of bit lines 112-114 detects the difference between the voltages on the two bit lines, and amplifies that difference using a cross-coupled amplifier 118 to generate a data out signal.
Since each read operation destroys the data stored in the cells 102-104, a data regeneration circuit 120 is used to rewrite that data back into the cells. More particularly, the read operation puts both cells 102-104 in the "0" state, and a "1" state is restored in one of the two cells by asserting a high voltage (e.g., 5 volts) signal on the corresponding bit line 112 or 114 and a low voltage (e.g., zero volts) on drive line 108.
Other aspects of the memory device include a word line address decoder 122 which decodes a portion of the incoming address signals into word line selection signals, and a control circuit 124 which controls the timing of various clock signals required for operating the memory device.
As shown in FIG. 1, each cell 102 contains a ferroelectric capacitor 130 and an MOS access control transistor 132. FIG. 2 shows the hysteresis curve (showing the relationship between polarization and electric field) associated with a typical ferroelectric capacitor. As will be understood by those skilled in the art, this hysteresis curve is generated using a "Sawyer-Tower" circuit. For illustrative purposes we shall define that when the cell is in the "0" state, the polarization state of the ferroelectric capacitor is located at point 140 and when it is in the "1" state its polarizatoin state is located at point 142 in FIG. 2.
When a read pulse is asserted on the cell's drive line 108, if the cell is the "1" state, the polarization of its ferroelectric capacitor will move counterclockwise up the right side of the hysteresis curve to the peak 144 while the pulse is at its peak, and then when the pulse ends, the ferroelectric capacitor will move to point 140. If the cell is in the "0" state when the read pulse is asserted, the polarization of the capacitor will move back up toward the peak 144 and then back to point 140 after the pulse ends. Changes in the polarization state of the cell's ferroelectric capacitor generate voltage changes on the cell's bit line by capacitive division with the bit line's parasitic capacitance.
Thus, as shown in FIG. 3, if the cell is in a "1" state, the read pulse "should" cause the output voltage of the cell to increase by an amount proportional to .DELTA.P1 (i.e., the polarization difference between positions 140 and 142). If the cell is in a "0" state, the read pulse "should" not cause the cell's bit line voltage to change at all. Unfortunately, the actual voltage characteristics of ferroelectric change at all. Unfortunately, the actual voltage characteristics of ferroelectric cells are different from the "ideal" hysteresis curve shown in FIG. 2. When the ferroelectric capacitor is first released from point 144, it actually follows path 146 to a point 148, and from there it relaxes back to point 140 over a period of time, which varies somewhat unpredictably from device to device, but will typically take somewhere between 100 nanoseconds and 1 millisecond.
The net result of all this is that when a ferroelectric cell in the "0" state is read, it produces a net voltage output proportional to .DELTA.P0 (i.e., the polarization difference between positions 148 and 140) if the output of the cell is read quickly (e.g., within ten or twenty nanoseconds of the time that the cell is pulsed). This presents a problem for the prior art memory device shown in FIG. 1 in that the signal differential between the two bit lines will be less than expected. However, if the two cells 102-104 could be relied upon to have identical device characteristics, this problem would not be significant.
Unfortunately, it is a well known fact that the device characteristics of ferroelectric cells vary considerably even though the cells are formed on the same monolithic integrated circuit. In particular, the shape of the hysteresis curves of cells changes over time, and changes somewhat based on the voltage stored in the cells over time. Since the two complementary cells used in prior art devices store opposite data, the two cells will age differently and their device characteristics become more and more different over time. In a certain percentage of cell pairs, the voltage corresponding to .DELTA.P0 of one cell will equal or exceed the voltage corresponding to .DELTA.P1* (i.e., the polarization difference between positions 148 and 142) of the other cell, thereby causing the sense amplifier to misread the stored data. This problem is particularly insidious because it typically does not show up until the memory device has been in operation for a period of time, such as a year, making it difficult to avoid through the use of device testing procedures. The problem is also difficult to solve because it is a statistical phenomenon with a high enough rate of occurrence that it makes it virtually impossible to make reliable high density memory devices with, say, over a few thousand bits per device (although future improvements in the materials used to manufacture such cells may lessen these problems).
In summary, prior art ferroelectric memory devices such as the one shown in FIG. 1 have the problem that the two cells used to store each bit of data age differently and have different hysteresis curves, making data sensing unreliable. The voltage output by one cell in a "0" state can actually exceed the voltage output by another cell in the "1" state. Furthermore, the prior art devices use two cells to store a single bit of data, which is not space efficient.